| Project Domains | Mentors | Project Difficulty |
|---|---|---|
| Computer Architecture, FPGA, Digital Design | Atharva Kashalkar, Saish Karole | Hard |
Project Description
SRA hosts its own 32-bit RISC-V Core, supporting the IM extensions. Currently compatible with an open-source toolchain, our core is poised for greater versatility.
This project aims to integrate our RISC-V core into the Xilinx Vivado ecosystem, allowing users to effortlessly drag and drop it into their designs as a soft core. Additionally, we aim to rigorously verify the RISC-V core using industry-standard methods for testing digital designs. Ensuring the core’s reliability and performance will provide a robust solution for a wide range of applications.
Resources
Inside a CPU
What is RISC-V?
What is a FPGA
MicroBlaze Processor
Verification of a CPU