Synapse32

Design, implement, and verify a direct-mapped and set-associative cache subsystem for an existing RISC-V pipeline—boosting performance through reduced memory-access latency.

Project Domains Mentors Project Difficulty
Computer Architecture, Verilog, Cache Design, RTL Shri Vishakh, Sujal Hard

Project Description

This project guides you from basic digital-logic foundations to a fully integrated cache inside a RISC-V core.
You’ll master Verilog for RTL design, explore cache theory (hits, misses, write policies, replacement strategies), and build two concrete implementations:

  • Direct-Mapped Cache – write-back, write-allocate policy with tag/data arrays, valid bits, and a write-back engine.
  • 2-Way Set-Associative Cache – adds an LRU replacement finite-state machine for improved miss behavior.

The final deliverable is a synthesizable cache subsystem plugged into the CPU pipeline, complete with test-benches, hit/miss statistics, and cycle-count comparisons against an uncached baseline.

Resources

Synapse32 RISC-V Core
Cornell CS3410 Cache Slides (2019)
Onur Mutlu — Cache Design Talk